In digital systems, items of information are stored in memory cells, such as in ROM (Read-Only Memory) memory cells, for example. Depending on the memory requirement, individual ROM memory cells can be used for this purpose, but in general ROM memories having arrangements (arrays) of ROM memory cells with crossed word and bit lines are used. The ROM memory cells are situated at the crossover points of word and bit lines and have a defined programming state, that is to say that they represent a logic 0 or a logic 1, for example. Programmable ROMs are known, in the case of which the programming state can be impressed on the ROM memory cells during an explicit programming step after fabrication, and mask-programmable ROMs are also known, in the case of which the programming state is defined during a specific fabrication step of the semiconductor component or of the integrated circuit which has the ROM memory cells. In general, mask-programmable ROMs cannot be reprogrammed after fabrication.
FIG. 1a illustrates a ROM memory cell in accordance with the prior art. The ROM memory cell has a switching element in the form of an NMOS transistor, the source region of which is connected to earth GND and the gate region of which is connected to a word line WL. If a suitable signal is applied to the word line WL, then the transistor switches “on”, that is to say that the source region of the transistor is conductively connected to the drain region of the transistor and the drain region is connected to earth GND. In the present example, earth GND represents a logic 0 and a supply voltage VDD (not illustrated) represents a logic 1. The programming of the ROM memory cell takes place by virtue of the fact that the drain region of the transistor is or is not connected to a bit line BL0. In FIG. 1a, the drain region is connected to the bit line BL0 via an electrical connection 21, so that the ROM memory cell from FIG. 1a has the programming state logic 0.
In order to read out the items of information from a ROM memory having an arrangement (array) of ROM memory cells illustrated in FIG. 1a, a row of ROM memory cells is driven via a word line WL by the application of a suitable signal to the word line WL. The various ROM memory cells of the driven row are or are not connected to a respective bit line BL0 via the electrical connection 21 in accordance with their programming state. The ROM memory cell from FIG. 1a has the programming state logic 0 and connects the bit line BL0 to earth GND in the driven state. If the ROM memory cell has a programming state corresponding to a logic 1, then the electrical connection 21 is not formed, and the potential of the bit line BL0 is not altered by the ROM memory cell in the driven state.
Prior to the read-out, all the bit lines which are connected to the row of ROM memory cells to be read are firstly set to the potential VDD, for example, which corresponds to the logic 1. Depending on the system architecture, the bit lines may also be precharged to VDD/2 or earth GND. Directly prior to the driving of the row of ROM memory cells to be read and the read-out of the programming states of these ROM memory cells, the applied potential is decoupled from the bit lines and there remains on the bit lines a charge which leaves the latter essentially at the previously applied potential.
It is assumed below that the bit lines are precharged to the potential VDD. If the driven ROM memory cell assigned to a given bit line has the programming state logic 0, then the charge on the bit line is dissipated via the transistor of the ROM memory cell and the bit line essentially assumes the earth potential GND or the potential GND+Vth, where Vth is the voltage drop along the transistor of the ROM memory cell. If the driven ROM memory cell has the programming state logic 1, then the charge remains on the bit line and the bit line essentially retains the precharged potential VDD.
In other system architectures, the bit lines are precharged to earth GND and, during read-out, in a first programming state of the driven transistor, charge flows onto the bit line and charges the latter to the potential VDD, for example. In a second programming state of the driven transistor, the bit line is not charged and it remains at the earth potential GND.
There is in each case a sense amplifier situated on the various bit lines, which sense amplifier senses the voltage of the respective bit line BL0 and determines from this the programming state of the driven ROM memory cell.
FIG. 1b shows a plan view of the layer structure of the ROM memory cell illustrated schematically in FIG. 1a. The word line WL runs horizontally in FIG. 1b, is formed from polysilicon and crosses a diffusion region, thus giving rise to a transistor with a source, gate and drain region. In order to improve the electrical properties of the word line WL formed from polysilicon, a metallic interconnect WL′ may additionally be provided, WL and WL′ being electrically connected at specific intervals (not illustrated). The source region of the transistor is connected to earth GND, it being possible for the earth line to be designed as a diffusion region. In order to improve the electrical properties, the earth line may additionally be provided with a further metallic interconnect. The bit line BL0 is designed as a metallic interconnect and runs vertically in FIG. 1b. The programming of the ROM memory cell takes place via a contact connection 21, which is or is not formed in accordance with the programming state of the ROM memory cell. The contact connection 21 connects the drain region of the transistor to the bit line BL formed in the metallization layer Metal 1. If the ROM memory cell is intended to assume the programming state logic 0, then the contact connection 21 is formed, as is illustrated in FIG. 1b. If the ROM memory cell is intended to assume the programming state logic 1, then the contact connection 21 is not formed, and the transistor of the ROM memory cell is not electrically connected to the bit line BL0.
The ROM memory may also be of the opposite construction in terms of voltage technology. In the ROM memory cells, a PMOS transistor is then used instead of the NMOS transistor, the source region of the transistor is connected to the supply voltage VDD instead of to earth GND, and the bit lines have the earth potential GND directly prior to the driving of a row of ROM memory cells to be read.
FIG. 2 illustrates the layer structure of a further ROM memory cell that is known in the prior art. This ROM memory cell is largely identical to the ROM memory cell discussed above. Parts having essentially similar functions are provided with the same reference symbols as in FIG. 1b. In contrast to the previous ROM memory cell, the contact connection 21 is always formed, independently of the intended programming state. In the case of this ROM memory cell, the programming takes place in a different production step. In accordance with the intended programming state, a diffusion region 22 is or is not formed below the word line WL. Consequently, a complete and functional transistor is formed only in one of the two possible programming states. In terms of voltage technology, this “diffusion-programmed” ROM memory cell behaves similarly to the ROM memory cell illustrated in FIGS. 1a and 1b. 
The published patent application DE 101 56 742 A1 discloses a further embodiment of a ROM memory cell. In this case, the programming takes place by means of an electrical connection between the source region of the transistor of the ROM memory cell and the earth line, which is or is not formed in a manner dependent on the intended programming state. In terms of voltage technology, this ROM memory cell behaves similarly to the two previously discussed known ROM memory cells from the prior art.
What is disadvantageous about the ROM memory cells known from the prior art is the relatively high outlay required to distinguish between the two programming states during read-out, said programming states being represented on the one hand by a defined potential (e.g. GND+Vth) and on the other hand by a potential which is not defined (biased) on a bit line. This requires a narrow sensing window, is relatively slow with regard to the read-out speed (performance) and makes the ROM memory, particularly in the case of potentials which are not defined (floating) on the bit lines, susceptible to crosstalk (or x-talk).